VT8601 Via, VT8601 Datasheet - Page 82

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

SRE – Mode Control 1 (Old) ............................................ RW
SRE – Mode Control 1 (New) ........................................... RW
Revision 1.3 September 8, 1999
2-1
5-0
7
6
5
4
3
0
7
6
7HFKQRORJLHV ,QF
Reserved
IRQ Polarity Select
Configuration Port (SR0C) Select
Reserved
Memory Bus .........................................................RO
256K Bank Select
Note: an inverted value will be written to bit-1
These bits (and 3C2[5]) are write enabled when
GR06[3-2] = 00. 3C2[5] is used as a page select to
select one of the two 64KB pages.
RAMDAC Pixel Clock Invert
Configuration Port Write Enable ........... default = 0
Ports effected: SRC, SRF, CR28-2A, SRE_New[6-4]
(this register), and SR10[0]
CPU Bandwidth Select for Text Mode
64K Bank Select ....................................... default = 0
Bit-1 should be inverted when performing writes
These bits are enabled when GR06[3-2] are written
with any value other than 00.
:H &
:H &R R QQHFW
00 Bank 0 ....................................................default
01 Bank 1
10 Bank 2
11 Bank 3
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Active High ............................................default
Active Low
Select Port 2
Select Port 1 ..........................................default
8-bit
16-bit .......................................always reads 1
Normal ...................................................default
Invert pixel clock to RAMDAC
Write Protect
Write Enable
132-Column Text
Other Text .............................................default
.......................................always reads 1
........................................ always reads 0
-76
SRF – Power-up Mode 2 .................................................. RW
This register is write protected by SRE_New[7].
SR10 – VESA™ Big BIOS Control ................................. RW
Bit-0 of this register is write protected by SRE_New[7].
SR11 – Protection
SR12 – Threshold
The old threshold is used when neither playback nor capture is
enabled.
definitions are the same as the original.
3-0
6-5
4-1
7-0
7-4
3-0
7
6
5
4
7
0
Reserved
BIOS Control
Palette Mode
Linear / Bank Addressing Control
Reserved for BIOS ............................ default = 1111
Extended VESA™ Big BIOS Enable
Video Address Select ........................................... RO
These bits are decoded from GR6[3-2]
Reserved
Page Select
Register Protection Enable ....................default = 00
If any value other than the ones listed above is
programmed into this register, all extended registers
will be write protected.
Queue Threshold Playback and Capture .....def = 2
Threshold of the display queue when both playback
and capture are enabled (for definition see SRD.new).
Queue Threshold Playback or Capture........def = 1
Threshold of the display queue when either playback
or capture are enabled (for definition see SRD.new)
All three thresholds cannot be set to 0.
00 A0000-A7FFF ....................................... default
01 -reserved-
10 B0000-B7FFF
11 B8000-BFFFF
87 Unprotect all extended registers except those
92 Unprotect all extended registers independent
0
1
0
1
0
1
0
1
0
1
Disabled................................................. default
Enabled
Master Abort Mode
Intel Retry Mode................................... default
Linear Only
Linear / Bank ........................................ default
Disabled ................................................ default
Enabled
Select the original C0000-C7FFF access ..... def
Select extended access defined by bits 6-5
which may still be protected by SRE_New[7]
of SRE_New[7]
...................................... always reads 1
........................................always reads 0
........................................................ RW
........................................................ RW
VT8601 Apollo ProMedia
VGA Extended Registers
Other