VT8601 Via, VT8601 Datasheet - Page 51

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 0 Offset 72 - CPU to PCI Flow Control 2 ......... RWC
Revision 1.3 September 8, 1999
5-4
7
6
3
2
1
0
7HFKQRORJLHV ,QF
Retry Status
Retry Timeout Action
Retry Limit
Clear Failed Data and Continue Retry
CPU Backoff on PCI Read Retry Failure
Reduce 1T for FRAME# Generation
Reduce 1T for CPU Read of PCI Slave
:H &
:H &R R QQHFW
00 Retry 2 times ..........................................default
01 Retry 16 times
10 Retry 4 times
11 Retry 64 times
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Retry occurred less than retry limit ........default
Retry occurred more than x times (where x is
defined by bits 5-4) .................write 1 to clear
Retry Forever (record status only)..........default
Flush buffer for write or return all 1s for read
Flush the entire post-write buffer ...........default
When data is posting and master (or target)
abort fails, pop the failed data if any, and keep
posting
Disable ...................................................default
Backoff CPU when reading data from PCI and
retry fails
Disable ...................................................default
Enable
Disable ..................................................Default
Enable
-45-
Device 0 Offset 73 - PCI Master Control 1 ..................... RW
Device 0 Offset 74 - PCI Master Control 2 ..................... RW
1-0
3
7
6
5
4
3
2
1
0
7
6
5
4
2
Reserved
PCI Master 1-Wait-State Write
PCI Master 1-Wait-State Read
Disable Prefetch when Doing Delay Transaction
Assert STOP# after PCI Master Write Timeout
Assert STOP# after PCI Master Read Timeout
LOCK# Function
PCI Master Broken Timer Enable
PCI Master Read Prefetch by Enhance Command
PCI Master Write Merge
Reserved
Dummy Request Handling............Should be set to 1
PCI Delay Transaction Time-Out
Backoff CPU Immediately on CPU to AGP Retry
CPU/PCI Master Latency Timer Control
00 AGP Master Reloads MLT timer........... default
01 Falling edge of AGP Master Request reloads
10 Rising Edge of AGP Master Request clears
11 Reserved (illegal setting)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Zero wait state TRDY# response........... default
One wait state TRDY# response
Zero wait state TRDY# response........... default
One wait state TRDY# response
Enable .................................................... default
Disable
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable. Force into arbitration when there is no
FRAME# 16 PCICLK’s after the grant. Does
not apply to south bridge PREQ# input
Always Prefetch..................................... default
Prefetch only if Enhance command
Disable................................................... default
Enable
As VP3................................................... default
Complete Fix
Disable................................................... default
Enable
Disable................................................... default
Enable
MLT timer
MLT timer and falling edge reloads the timer
........................................always reads 0
........................................always reads 0
Device 0 Bus 0 Host Bridge Registers
VT8601 Apollo ProMedia