VT8601 Via, VT8601 Datasheet - Page 99

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

CR2B – Horizontal Parameter Overflow ........................ RW
CR2D – GE Timing Control ............................................. RW
CR2F – Performance Tuning ........................................... RW
Revision 1.3 September 8, 1999
7-5
7-5
4-3
2-0
3-2
4
3
2
1
0
7
6
5
4
1
0
7HFKQRORJLHV ,QF
Reserved
Horizontal Blank Start Bit-8................... default = 0
Horizontal Retrace Start Bit-8 ............... default = 0
Horizontal Interlace Parameter Bit-8 ... default = 0
Horizontal Display Enable Bit-8 ............ default = 0
Horizontal Total Bit-8 ............................ default = 0
Reserved
GE Sample Clock Delay Selection .......... default = 0
GE Frame Buffer Read Delay Cycles..... default = 0
Reserved
DRAM Refresh Cycle Control Bit-1
(Bit-0 is CR11[6])
Blank TimingSelect
Display FIFO Depth Control
Memory Read Ready Control
Clock Source
Pin Scan (Test Only) ................................ default = 1
:H &
:H &R R QQHFW
00 3 refresh cycles per horizontal line
01 5 refresh cycles per horizontal line
10 1 refresh cycles per horizontal line
11 2 refresh cycles per horizontal line
00 -reserved.................................................default
01 Fast read cycle (same as 10)
10 Fast read cycle (same as 01)
11 Normal read cycle
0
1
0
1
0
1
QQHFW
Normal blank..........................................default
Blank is the inverse of display enable
32 deep ...................................................default
8 deep
VCLK2
VCLK1 ..................................................default
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
-93
CR35-34 – Graphics Engine I/O Linear Address Base . RW
CR36 – Graphics Engine / Video Engine Control .......... RW
CR37 – I
15-0 Graphics Engine Linear Address Base ... default = 0
1-0
5-4
7
6
5
4
3
2
7
6
3
2
1
0
Graphics Engine
PCI Video Minifier
Video Aperture
Graphics Engine Software Reset
Writing a one to this bit resets the graphics engine
Graphics Engine I/O
String Write
Graphics Engine Register Mapping
SMBCLK Buffer is Open Drain........ always reads 1
I
Reserved
I
Reserved
I
I
2
2
2
2
2
C / SMB Control .............................................. RW
C SMBCLK Status ............................................RO
C Operation
C SMBCLK Signal
C SMBDAT Signal
00 I/O mapped at 21xxh ............................. default
01 Memory mapped at B7Fxxh
10 Memory mapped at BFFxxh
11 Memory mapped using the GE base register
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disable................................................... default
Enable
Bypass ................................................... default
Go through minifier
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Read .................................................... default
Write
Low
High ................................................... default
Low .................................................... default
High
........................................ always reads 0
........................................ always reads 0
VT8601 Apollo ProMedia
VGA Extended Registers