VT8601 Via, VT8601 Datasheet - Page 123

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Setup Engine Registers
GEbase + 30 – Setup Engine Primitive Attribute ........... RW
Revision 1.3 September 8, 1999
24-20 Reserved
19-15 LOD Adjust .............................................. default = 0
14-7 Reserved
31
30
29
28
27
26
25
7HFKQRORJLHV ,QF
Z Parameter
Texture Parameter
Perspective Factor Parameter
Color Parameter
Specular Color Parameter
Fog Parameter
Step Mode
3.2 signed # to be added to calculate the LOD value
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Absent ....................................................default
Present (Setup Engine calculates Z slope)
Absent ....................................................default
Present (SE calculates Z slope)
Absent ....................................................default
Present (SE calculates W slope)
Absent ....................................................default
Present (SE calculates color slope)
Absent ....................................................default
Present (SE calculates specular slope)
Absent ....................................................default
Present (SE calculates fog slope)
Disable ...................................................default
Enable (SE will process the next primitive only
when it finishes the current primitive. There is
no parallelism between primitives)
........................................ always reads 0
........................................ always reads 0
-117
This register is decoded by the Setup Engine and passed to the
Rasterization Engine by the Setup Engine. This register and
its equivalent part in the Rasterization Engine are “partially”
pipelined in the sense that there are only two levels of pipe for
this register in both engines while there are many levels for
other data. The two levels are the decoding level and the
execution level. Both the Rasterization Engine and the Setup
Engine use this register to decide what kind of operation to
perform and what kind of data stream to expect. It must be set
before any parameter can be loaded.
6
5
4
3
2
1
0
Z Normalization (Setup Engine Only)
Flat Mode (applies to diffuse color, alpha, specular
color, and fog)
Full Vertex Info
Sub-Pixel Precision (Rasterization Engine Only)
Anti-Aliasing (RE Only)
Auto Direction for Scan Line Ends (RE Only)
Bresenham Edge Walking (RE Only)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disable................................................... default
Enable
Smooth color or no color ....................... default
Flat color. SE sends only starting values to RE
Disable................................................... default
Enable.
needed for the triangle. Software still needs to
set bits 31-25. However in this case, the data
order in a vertex is: X, Y, Z, W, RGBA,
SrgbF, U, V. Even though the vertex actually
contains all the data, software doesn’t
necessarily set this bit. When this bit is not
set, hardware decodes vertex data as described
in the Vertex Register descriptions.
Disable................................................... default
Enable
Disable (walk at pixel precision) ........... default
Enable (walk at sub-pixel precision)
Disable................................................... default
Enable. Bits 31-2 must be 0. Scan order is
passed to the Pixel Engine based on the
comparison result of two end points instead of
the bit in the Primitive Type register. Software
should only use this bit for 2D polygons with
Bresenham edge walking.
Use DDA to walk through edges ........... default
Use Bresenham algorithm to walk through
edges
VT8601 Apollo ProMedia
Indicates that all vertex data are
3D Graphics Engine Registers