VT8601 Via, VT8601 Datasheet - Page 76
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VT8601
Manufacturer Part Number
VT8601
Description
Slot-1 / Socket-370 PCI North Bridge
Manufacturer
Via
Datasheet
1.VT8601.pdf
(144 pages)
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VGA Registers
Attribute Controller Registers (AR)
For this indexed register group, the index is accessed at 3C0
as expected.
performed using port 3C1 in the standard way, data is
generally accessed at 3C0 as well. In other words, data and
address are accessed on alternate operations to 3C0 with an
internal flag to keep track of where the next operation is to be
performed. The state of the internal flag may be read back in
the extended registers (see CR24). To set the internal flag to
select the index (i.e., to set the flag so that the next access to
port 3C0h points to the index register), read port 3BAh or
3DAh (depending on the state of the color / mono bit in the
Miscellaneous Output Register at 3C2[0]).
Controller register data may be read at 3C1 (the internal flag is
not toggled) but must be written at 3C0.
Port 3C0 – VGA Attribute Controller Index .................. RW
Port 3C0/3C1 Index 0-F – Attr Ctrlr Color Palette ....... RW
Port 3C0/3C1 Index 10 – Attr Ctrlr Mode Control ....... RW
Port 3C0/3C1 Index 11 – Attr Ctrlr Overscan Color ..... RW
Port 3C0/3C1 Index 12 – Attr Ctrlr Color Plane Ena ... RW
Port 3C0/3C1 Index 13 – Attr Ctrlr H Pixel Panning .... RW
Port 3C0/3C1 Index 14 – Attr Ctrlr Color Select ........... RW
Revision 1.3 September 8, 1999
7-6
4-0
7-6
5-0
7-0
7-6
5-4
3-0
7-4
3-0
7-4
3-0
5
7
6
5
4
3
2
1
0
7HFKQRORJLHV ,QF
Reserved
Palette Address Source
Attribute Controller Index
Only the lower 5 bits are implemented to allow access
to Attribute Controller registers 0-14h.
Reserved
Color Value
P5 / P4 Select
Pixel Width
Pixel Panning Compatibility
Reserved
Select Background Intensity or Enable Blink
Enable Line Graphics Character Mode
Display Type
Graphics / Text Mode
Overscan Color
Reserved
Video Status Mux
Color Plane Enable for Color Planes 3-0
Reserved
Horizontal Pixel Pan
Reserved
Color Select Bits 7-4
:H &
:H &R R QQHFW
QQHFW
However, although data operations can be
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
Attribute
-70
VGA Status / Enable Registers
Port 3C2 – VGA Input Status 0 ........................................ RO
Port 3xA – VGA Input Status 1 ........................................ RO
This register is accessible at either 3BA or 3DA (shorthand
notation 3xA) depending on the setting of Miscellaneous
Output Register at 3C2[0].
Port 3C2 – VGA Miscellaneous Output Register (Write) WO
Port 3CC – VGA Miscellaneous Output Register (Read) RO
Port 3C3 – VGA Video Subsystem Enable ..................... RW
Port 46E8h – VGA Display Adapter Enable .................. RW
6-5
3-0
7-6
5-4
2-1
3-2
7-1
7-4
2-0
7
4
3
0
7
6
5
4
1
0
0
3
Vertical Retrace Interrupt Pending
Reserved
Switch Sense
Reserved
Reserved
Diagnostic
Vertical Retrace
Reserved
Display Enable (Inverted)
Vertical Sync Polarity
Horizontal Sync Polarity
Page Bit for Odd / Even
Reserved
Clock Select
Enable RAM
I/O Address Select
Reserved
Video Subsystem Enable
Reserved
Display Adapter Enable
Reserved
0
1
CRTC registers at 3Bx, Input Status 1 at 3BA
CRTC registers at 3Dx, Input Status 1 at 3DA
........................................ always reads 0
........................................always reads 0
........................................ always reads 0
........................................always reads 0
........................................always reads 0
........................................always reads 0
........................................always reads 0
........................................always reads 0
VT8601 Apollo ProMedia
VGA Registers