VT8601 Via, VT8601 Datasheet - Page 106

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

CR8F-8E – Video Display Engine Flags .......................... RW
CR91-90 – Window 1 / W1-Y Row Byte Offset .............. RW
CR94-92 – Window 1 / W1-Y Video Start Address ........ RW
Revision 1.3 September 8, 1999
15-14 Reserved
23-21 Reserved
13-0 Video Row Byte Offset
19-0 Video Start Addres (in bytes)
7-5
2-1
15
14
13
12
11
10
20
9
8
4
3
0
7HFKQRORJLHV ,QF
Planar Capture Mode
VSYNC Test / Graphics Engine Reset
Edge Recovery Algorithm Control
Window 1 Vertical Interpolation
Window 1 Horizontal Interpolation
CSC / Bypass Select
Line Toggle for Line Buffer
Reserved
Window 1 HDEO Delay Adjust .............. default = 4
Video Window 1
CCIR-/ DTV Input Video Data Control
W1 / W2 Line Buffer Page Break Level Control
Video Window 2
Programmed with the number of bytes in a row
Used with CR97 bit-7
:H &
:H &R R QQHFW
00 8 levels ...................................................default
01 16 levels
1x 32 levels
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Planar 420 Capture.................................default
Planar 422 Capture
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
CSC .....................................................default
Bypass
Normal ...................................................default
Toggle (Reversed)
Disable ...................................................default
Enable
CCIR Format ..........................................default
DTV Format
Disable ...................................................default
Enable
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
-100
CR95 – Video Window Line Buffer Threshold .............. RW
CR96 – Window 1 / W1-Y Line Buffer Level Control .. RW
CR97 – Video Display Engine Flags ................................ RW
CR9A-98 – Capture Video Start Address ....................... RW
23-20 Reserved
19-0 Capture Video Start Address
6-0
7-0
7
7
6
5
4
3
2
1
0
Line Buffer Level Bit-8 (used with CR96)
W1 / W2 Line Buffer Request Threshold Value
When the line buffer is less than this value, a memory
request will be issued. The value programmed in this
register must be less than the line buffer level (see bit-
7 and CR96).
Line Buffer Levels (bit-8 is in CR95[7])
RGB8: (pixel # + 2) / 8 rounded up
YUV 4:2:2: (Pixel # + 2) / 4 rounded up
For W1-U or W1-V, the level is this value divided by
4 or 16, depending on the panar format (YUV12 or
YUV9)
Start Address Reload Control
Video Start Reference Select
Address Point Invert
Odd / Even Invert (Anti-tearing)
Playback Test Mode Select (RGB Data Select)
Playback Test Mode
Anti-tearing Sync Select
Anti-tearing
This bit is automatically disabled if there is only one
video stream and dual live video mode is enabled. In
this mode, the even field is used for one live video
stream and the odd field is used for the other live
video stream.
Controlled by SRBE (3C5 index BE).
0
1
x
0
1
0
1
0
1
0
1
0
1
0
1
CR94[4]=0 address can be reloaded any time
CR94[4]=0 only reloaded during Vsync
CR94[4]=1 address not reloaded
HSYNC / VSYNC ................................. default
Use fixed signals (fixed relationship with HDE
and VDE) as video start reference
Normal................................................... default
Invert
Normal................................................... default
Invert
Disable................................................... default
Enable
VGA Vsync ........................................... default
Playback Vsync
Disable................................................... default
Enable
........................................ always reads 0
VT8601 Apollo ProMedia
VGA Extended Registers