VT8601 Via, VT8601 Datasheet - Page 42

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 0 Bus 0 Host Bridge Registers
CPU Interface Control
Device 0 Offset 50 – Request Phase Control (00h) ......... RW
Revision 1.3 September 8, 1999
3-2
7
6
5
4
1
0
7HFKQRORJLHV ,QF
CPU Hardwired IOQ (In Order Queue) Size
Default per strap on pin MA11 during reset. This
register bit can be written to 0 to restrict the chip to
one level of IOQ.
Read-Around-Write
Reserved
Defer Retry When HLOCK Active
Note: always set this bit to 1
Reserved
Fast Speculative Read
CPU / PCI Master Read DRAM Timing
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
0
1
QQHFW
1-Level
4-Level ....... default if no external strap resistor
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Start DRAM read after snoop complete ...... def
Start DRAM read before snoop complete
........................................ always reads 0
........................................ always reads 0
-36-
Device 0 Offset 51 – Response Phase Control (00h)....... RW
7
6
5
4
3
2
1
0
CPU Read DRAM 0WS for Back-to-Back Read
Transactions
Setting this bit enables maximum read performance
by allowing continuous 0-wait-state reads for
pipelined line reads. If this bit is not set, there will be
at least 1T idle time between read transactions.
CPU Write DRAM 0WS for Back-to-Back Write
Transactions
Setting this bit enables maximum write performance
by allowing continuous 0-wait-state writes for
pipelined line writes ands sustained 3T single writes.
If this bit is not set, there will be at least 1T idle time
between write transactions.
DRAM Read Request Rate
Fast Response (HIT/HITM Sampled 1T Earlier)
Non-Posted IOW
CPU Read DRAM Prefetch Buffer Depth
CPU-to-DRAM Post-Write Buffer Depth
Concurrent PCI Master / Host Operation
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disable................................................... default
Enable
Disable................................................... default
Enable
3T
2T
Disable................................................... default
Enable
Disable................................................... default
Enable
1-level prefetch buffer ........................... default
4-level prefetch buffer
1-level post-write buffer ........................ default
4-level post-write buffer
Disable – the CPU bus will be occupied (BPRI
asserted) during the entire PCI operation..... def
Enable – the CPU bus is only requested before
ADS# assertion
.................................................... default
Device 0 Bus 0 Host Bridge Registers
VT8601 Apollo ProMedia