VT8601 Via, VT8601 Datasheet - Page 113

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Drawing
Bitblt - Frame Buffer to Frame Buffer
Blt operation may involve a pattern. If it does, and the pattern
is stored in the frame buffer, the pattern parameters (P1, P2,
P3) must also be set. The following registers must be set to
provide the source and destination rectangles of blt: Ps1, Pd1,
Ps2, and Pd2. These registers can be set in any order. If a
register is set several times, only the last one is effective.
After all the registers are set, the program starts blting by
writing a blt command to Command Register.
Bitblt - CPU to Frame Buffer
The operation for blting from the CPU is similar to the blting
from the frame buffer except that Ps1 and Ps2 are not needed
and the data from the CPU must immediately follow the
setting of the Command Register.
For all commands that require data from the CPU, the
command and data are considered atomic; i.e., the data should
follow the command immediately and no other command or
parameter can be placed in between. The data can be written
to Data Register III and IV. Alternatively, it can be written to
a memory-mapped space designated by ProMedia apertures.
The same rule applies to drawing text from the CPU to the
frame buffer.
Text
Text glyph can be from the CPU or the frame buffer. When
the glyph is from the CPU, the registers to be set are Pd1 and
Pd2 for text location. When the glyph is stored in the frame
buffer, the registers to be set are Ps1, Ps2, Pd1, and Pd2 to
provide both the glyph and text locations. These registers can
be set in any order. If a register is set several times, only the
last one is effective. After all the registers are set, the program
starts blting by writing a text command to Command Register.
The major difference between text and Blt is that a text source
data is 8-bit aligned while the bitblt is 64-bit aligned. That is,
for text, each new line starts at the byte boundary, while for a
bitblt, at the 64-bit boundary.
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A Note on CPU as the Source of Operation
Any operation that uses the CPU as the source of operation
(such as the Blt shown in section x) requires the host CPU to
feed data into data registers III and IV (BA+56 and 60). Since
the ProMedia is using the 64-bit internal data path, any data
(32-bit) from the CPU will be packed into 64-bit before use.
Therefore, there are two registers for the CPU to write. These
two registers are arranged as shown in the following diagram.
Writing to Data Register IV triggers data in both registers to
be sent to the engine for processing. However, the hardware
may expose the two registers as a mapped space to save
software from toggling between the two registers.
Geometry Primitive
To draw a geometry primitive, the host must issue a drawing
command by writing to the Command Register first and then
set up the geometry as described in later in this document.
VT8601 Apollo ProMedia
3D Graphics Engine Registers