VT8601 Via, VT8601 Datasheet - Page 62

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Offset 5-4 - Command ....................................................... RW
Revision 1.3 September 8, 1999
15-10 Reserved
9
8
7
6
5
4
3
2
1
0
7HFKQRORJLHV ,QF
Fast Back-to-Back Cycle Enable ........................ RO
SERR# Enable...................................................... RO
(SERR# is used to report parity errors if bit-6 is set).
Address / Data Stepping ...................................... RO
Parity Error Response......................................... RO
VGA Palette Snoop .............................................RW
Memory Write and Invalidate Command.......... RO
Special Cycle Monitoring .................................... RO
Bus Master .........................................................RW
Memory Space.....................................................RW
I/O Space
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Fast back-to-back transactions only allowed to
the same agent
Fast back-to-back transactions allowed to
different agents
SERR# driver disabled ...........................default
SERR# driver enabled
Device never does stepping....................default
Device always does stepping
Ignore parity errors & continue ..............default
Take normal action on detected parity errors
Treat palette accesses normally ..............default
Don’t respond to palette accesses on PCI bus
Bus masters must use Mem Write ..........default
Bus masters may generate Mem Write & Inval
Does not monitor special cycles .............default
Monitors special cycles
Never behaves as a bus master ...............default
Can behave as a bus master
Does not respond to memory space
Responds to memory space ....................default
Does not respond to I/O space
Responds to I/O space ...........................default
.........................................................RW
........................................ always reads 0
........... default set from inverse of MA??
-56
Offset 7-6 - Status .......................................................... RWC
10-9 DEVSEL# Timing
3-0
15
14
13
12
11
8
7
6
5
4
Device 0 Bus 1 Header Registers - Graphics Accelerator
Detected Parity Error
Signaled System Error (SERR# Asserted)
Signaled Master Abort (Bus Master Only)
Received Target Abort (Bus Master Only)
Signaled Target Abort........................ always reads 0
Data Parity Error Detected (Bus Master Only)
Fast Back-to-Back Capable
Reserved
66MHz Capable..................................always reads 1
Supports New Capability list............. always reads 0
Reserved
00 Fast
01 Medium....................................always reads 01
10 Slow
11 Reserved
0
1
0
1
0
1
0
0
1
0
1
No parity error detected ......................... default
Error detected in either address or data phase.
This bit is set even if error response is disabled
(command register bit-6). ......write one to clear
No abort received .................................. default
Transaction aborted by the master ...................
No abort received .................................. default
Transaction aborted by the target......................
Target Abort never signaled
No data parity error detected .....always reads 0
Error detected in data phase
Not capable............................................ default
Capable
........................................ always reads 0
....................................write one to clear
....................................... write 1 to clear
........................................ always reads 0
........................................always reads 0
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