VT8601 Via, VT8601 Datasheet - Page 92

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Power Management Registers
GR20 – Standby Timer Control ....................................... RW
GR21 – Power Management Control 1 ........................... RW
Revision 1.3 September 8, 1999
6-4
3-0
7
7
6
5
4
3
2
1
0
7HFKQRORJLHV ,QF
Timer Initialize & Enable
Timer Testing .......................................................RO
Reserved
Power Management Pin Polarity
PCI Power Management
Suspend Mode
Suspend Input Pin
D3 to D0 Reset
Standby Input Pin
CLKRUN# Mechanism
Consistent Standby / Suspend
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Enable Timer..........................................default
Initialize and hold standby and DPMS timer
Active High ............................................default
Active Low
Disable ...................................................default
Enable
Normal mode..........................................default
Enter Suspend Mode
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
The bits in the PCI PM configuration registers
will be OR’ed with bits 5 and 3 of this register
for connection to the internal PM state
machine ..................................................default
The bits in the PCI PM configuration registers
will be the same as bits 5 and 3 of this register
to allow software coherency
........................................ always reads 0
-86
GR22 – Power Management Control 2 ........................... RW
5-4
7
6
3
2
1
0
Timer Test Mode
Refresh Clock Select
Suspend DRAM Refresh Mode
Disable GPIO
Reserved
Hardware / Software Oscillator Select
Oscillator Disable
00 No refresh .............................................. default
01 Self refresh
10 Crystal clock provides rate for 8ms refresh
11 Crystal clock provides rate for 64ms refresh
0
1
0
1
0
1
0
1
0
1
Disable................................................... default
Enable
Crystal input or external clock (XMCLK)
provides refresh clock during suspend... default
REFCLK is used as refresh clock during
suspend for 64ms refresh (ignore “Suspend
DRAM Refresh Mode” bits 5-4 below)
Allow GPIO 7-0 pins to drive data in .... default
Disable GPIO 7-0 pins (and their shared
functions) from driving data. Tristates input
buffers on pins so no power is consumed if
GPIO pins are set to input mode.
Software controls oscillator off with bit-0
(prevents
without direct software control of the
“Oscillator Disable” bit) .............................. def
Hardware controls oscillator off (allow
oscillator shutdown when power states are
entered using hardware mechanisms)
Enable normal function.......................... default
Disable (oscillator off)
........................................ always reads 0
VT8601 Apollo ProMedia
automatic
VGA Extended Registers
oscillator
shutdown