VT8601 Via, VT8601 Datasheet - Page 47

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 0 Offset 64 - DRAM Timing for Banks 0,1 ......... RW
Device 0 Offset 65 - DRAM Timing for Banks 2,3 ......... RW
Device 0 Offset 66 - DRAM Timing for Banks 4,5 ......... RW
FPG / EDO Settings for Registers 64-66
SDRAM Settings for Registers 64-66
Revision 1.3 September 8, 1999
5-4
5-4
1-0
7
6
3
2
1
0
7
6
3
2
7HFKQRORJLHV ,QF
RAS Precharge Time
RAS Pulse Width
CAS Read Pulse Width
Note: EDO will not automatically reduce the CAS
pulse width. For EDO type DRAMs, use 00 if CAS
width = 1 is to be used.
CAS Write Pulse Width
MA-to-CAS Delay
RAS to MA Delay
Reserved
Precharge Command to Active Command Period
Active Command to Precharge Command Period
CAS Latency
Reserved (Do Not Program).................... default = 0
ACTIVE Command to CMD Command Period
Bank Interleave
:H &
:H &R R QQHFW
00 1T
01 2T
10 3T
11 4T
00 1T
01 2T
10 3T
11 Reserved
00 No Interleave..........................................default
01 2-way
10 4-way
11 Reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
3T
4T
4T
5T
1T
2T
1T
2T
1T
2T
T
T
T
T
2T
3T
RP
RP
RAS
RAS
= 2T
= 3T ................................................default
= 5T
= 6T ..............................................default
.....................................................default
.....................................................default
.....................................................default
.....................................................default
.....................................................default
.....................................................default
.....................................................default
........................................ always reads 0
.....................................................default
-41-
Device 0 Offset 68 - DRAM Control ............................... RW
1-0
7
6
5
4
3
2
SDRAM Open Page Control
Bank Page Control
EDO Pipeline Burst Rate
DRAM Data Latch Delay for EDO/FPG DRAM
EDO Test Mode
Note: MD0 is internally pulled up for EDO detection.
Burst Refresh
System Frequency Divider...................................RO
These bits are latched from MA[14, 12] at the rising
edge of RESET#.
resistors, the default setting of these bits is 00 (66
MHz).
00 CPU/PCI Frequency Ratio = 2x
01 CPU/PCI Frequency Ratio = 3x
10 CPU/PCI Frequency Ratio Auto Detect
11 CPU/PCI Frequency Ratio = 4x
0
1
0
1
0
1
0
1
0
1
0
1
Always precharge SDRAM banks when
accessing EDO/FPG DRAMs ................ default
SDRAM banks remain active when accessing
EDO/FPG banks
Allow only pages of the same bank active ... def
Allow pages of different banks to be active
X-2-2-2-2-2-2-2 ..................................... default
X-2-2-2-3-2-2-2
Latch DRAM data at CCLK rising edge..... def.
Delay latch of DRAM data by ½ CCLK
Disable................................................... default
Enable
Disable................................................... default
Enable (burst 4 times)
Device 0 Bus 0 Host Bridge Registers
VT8601 Apollo ProMedia
Without external strapping
(100 MHz)
(133 MHz)
(66 MHz)