VT8601 Via, VT8601 Datasheet - Page 24

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Signal Name
HCLK
MCLKI
MCLKO
PCLK
PCKRUN#
XLTI
XLTO
RESET#
CPURST#
CPURSTD#
PWROK
SUST#
SUSP
Signal Name
ETST#
IMIO
IMIIN
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AB15
AD14
AC22
AF15
AE15
Pin #
Pin #
G22
K22
A19
E22
J22
W4
M2
M3
Y4
F5
F4
I/O
I/O
IO
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Signal Description
Host Clock. This pin receives the host CPU clock. This clock is used by all logic in
the host CPU domain. It is driven by the external clock synthesizer.
Memory Clock In. This clock is used by internal clock logic to maintain the proper
phase relationship with MCLKO. It is driven by the external clock synthesizer.
Memory Clock Out. Created on-chip from MCLKI and used by the memory controller
as a timing reference for creation of all memory timing sequences. It is connected to the
external clock chip for use in maintaining proper phase relationships.
PCI Clock. This clock is used by all on-chip logic in the PCI clock domain. This input
must be 33 MHz maximum to comply with PCI specification requirements and must be
synchronous with the host CPU clock (HCLK) with an HCLK:PCLK frequency ratio of
2:1 (66MHz CPU clock) or 3:1 (100 MHz CPU clock). The PCI clock needs to be
controlled to within 1.5 ± 0.5 nsec relative to the host CPU clock (CPU leads).
PCI Clock Run. For implementation of PCI bus clock control for low-power PCI bus
operation. Refer to the “PCI Mobile Design Guidelines” and “Apollo ProMedia Design
Guide” documents for additional information.
Crystal Input. 14.31818 MHz for the video clock synthesizer reference. Connect to a
14.31818 MHz clock source if a crystal not used. Connect to main ground plane GND
with 10Pf if using a crystal.
Crystal Output. 14.31818 MHz for the video clock synthesizer reference. Leave open
if a clock source is used instead of a crystal. Connect to main ground plane GND with
10Pf if using a crystal.
Reset. Driven from the South Bridge PCIRST# signal. When asserted (low), this signal
resets the ProMedia and sets all register bits to the default value. This signal also
connects to the PCI bus (South Bridge RESET drives the ISA bus if implemented). The
rising edge of this signal is used to sample all power-up strap options (see memory
interface MA pins).
CPU Reset. CPU Reset output to the host CPU.
CPU Reset Delayed 2T. Alternate CPU Reset output to the host CPU
Power OK. Connect to South Bridge and Power Good circuitry.
Suspend Status. For implementation of the Suspend-to-DRAM feature. Input logic for
this pin is powered by VSUS. Connect to the South Bridge SUST# pin or to a 10K
pullup to VSUS if not used.
Suspend. Used to put the integrated graphics controller into suspend state.. Input logic
for this pin is powered by VSUS. Connect to South Bridge GPO pin or to a 10K
pullup to VSUS if not used.
Signal Description
Test Mode Enable. 4.7K pullup to VCC3 for normal operation.
IMI Out. Leave open.
IMI In. 4.7K pullup to VCC3.
Clock / Reset Control
Miscellaneous
-18-
VT8601 Apollo ProMedia
Pinouts