VT8601 Via, VT8601 Datasheet - Page 9
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VT8601
Manufacturer Part Number
VT8601
Description
Slot-1 / Socket-370 PCI North Bridge
Manufacturer
Via
Datasheet
1.VT8601.pdf
(144 pages)
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Revision 1.3 September 8, 1999
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Advanced High-Performance DRAM Controller
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DRAM interface synchronous or pseudosynchronous with CPU FSB speed of 66 / 100 / 133 MHz
DRAM interface may be faster than CPU by 33 MHz to allow use of PC100 with 66 MHz Celeron CPU or use of
PC133 with 100 MHz Pentium II or Pentium III CPU
DRAM interface may be slower than CPU by 33 MHz to allow use of older memory modules with a newer CPU
Concurrent CPU, AGP, and PCI access
Supports FP, EDO, SDRAM and VCM-SDRAM memory types
Different DRAM types may be used in mixed combinations
Different DRAM timing for each bank
Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems
Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs
6 banks DRAMs supported up to 1GB (256Mb DRAM technology)
Flexible row and column addresses
64-bit data width only
3.3V DRAM interface with 5V-tolerant inputs
Programmable I/O drive capability for MA, command, and MD signals
Two-bank interleaving for 16Mbit SDRAM support
Two-bank and four bank interleaving for 64Mbit SDRAM support
Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU
Independent SDRAM control for each bank
Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)
Four cache lines (16 quadwords) of CPU to DRAM write buffers
Four cache lines of CPU to DRAM read prefetch buffers
Read around write capability for non-stalled CPU read
Speculative DRAM read before snoop result
Burst read and write operation
x-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM from CPU or from DRAM controller
x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM
BIOS shadow at 16KB increment
Decoupled and burst DRAM refresh with staggered RAS timing
CAS before RAS or self refresh
-3-
VT8601 Apollo ProMedia
Features