MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 122

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Mode Registers
Figure 46: MRS to MRS Command Timing (
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Notes:
Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device
loses power.
Contents of a mode register can be altered by re-executing the MRS command. Even if
the user wants to modify only a subset of the mode register’s variables, all variables
must be programmed when the MRS command is issued. Reprogramming the mode
register will not alter the contents of the memory array, provided it is performed cor-
rectly.
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (
mand has been issued, two parameters must be satisfied:
ler must wait
Command
The controller must also wait
ing NOP and DES). The DRAM requires
with the exception of DLL RESET, which requires additional time. Until
satisfied, the updated features are to be assumed unavailable.
Address
1. Prior to issuing the MRS command, all banks must be idle and precharged,
2.
3. CKE must be registered HIGH from the MRS command until
4. For a CAS latency change,
CKE
CK#
must be satisfied, and no data bursts can be in progress.
t
er-Down Mode (page 169)).
CK
MRD specifies the MRS to MRS command minimum cycle time.
3
MRS
Valid
t
T0
MRD before initiating any subsequent MRS commands.
1
t
RP is satisfied and no data bursts are in progress). After an MRS com-
t
MRD)
NOP
T1
122
t
t
MOD before initiating any non-MRS commands (exclud-
XPDLL timing must be met before any non-MRS command.
1Gb: x8, x16 Automotive DDR3 SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
t
MOD in order to update the requested features,
T2
t
MRD
NOP
Ta0
t
MRD and
t
Indicates break
in time scale
MRSPDEN (MIN) (see Pow-
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NOP
Mode Registers
Ta1
t
MOD. The control-
t
MOD has been
t
RP (MIN)
Don’t Care
MRS
Valid
Ta2
2