MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 149

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MT41J64M16JT-15E AIT:G

Manufacturer Part Number
MT41J64M16JT-15E AIT:G
Description
DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
Manufacturer
Micron
Datasheet
Figure 68: READ (BC4) to WRITE (BC4) OTF
Command
Figure 69: READ to PRECHARGE (BL8)
DQS, DQS#
DQS, DQS#
Command
Address
Address
CK#
DQ
DQ 3
CK
CK#
CK
1
2
Bank a,
READ
Col n
T0
READ
Bank,
Col n
T0
READ-to-WRITE command delay = RL +
NOP
T1
NOP
T1
Notes:
NOP
T2
t
RAS
NOP
T2
t
RTP
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
RL = 5
NOP
T3
T4.
t
NOP
CCD/2 + 2
T3
NOP
T4
t
CK - WL
WRITE
T4
Bank,
Col b
Bank a,
(or all)
PRE
T5
t
RPRE
NOP
T5
NOP
T6
DO
n
DO
n + 1
NOP
T6
NOP
T7
n + 2
DO
WL = 5
t
RPST
n + 3
DO
NOP
NOP
T8
T7
DO
n
n + 1
DO
t
NOP
RP
T9
NOP
T8
n + 2
DO
t
WPRE
n + 3
DO
NOP
T10
n + 4
NOP
DO
T9
DI
n
n + 5
DO
n + 1
DI
NOP
T11
n + 6
DO
n + 2
NOP
T10
DI
n + 7
DO
n + 3
t
DI
T12
NOP
BL = 4 clocks
t
WPST
NOP
T11
Bank a,
Row b
ACT
T13
NOP
T12
T14
NOP
Transitioning Data
NOP
T13
T15
NOP
Transitioning Data
NOP
T14
NOP
T16
t
t
WTR
WR
Don’t Care
Don’t Care
NOP
NOP
T15
T17

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