MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 6

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

List of Figures
Figure 1: DDR3 Part Numbers .......................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 128 Meg x 8 Functional Block Diagram ............................................................................................. 14
Figure 4: 64 Meg x 16 Functional Block Diagram ............................................................................................. 15
Figure 5: 78-Ball FBGA – x8 (Top View) ........................................................................................................... 16
Figure 6: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17
Figure 7: 78-Ball FBGA – x8 (JP) ...................................................................................................................... 22
Figure 8: 96-Ball FBGA – x16 (JT) ................................................................................................................... 23
Figure 9: Thermal Measurement Point ........................................................................................................... 24
Figure 10: Input Signal .................................................................................................................................. 39
Figure 11: Overshoot ..................................................................................................................................... 40
Figure 12: Undershoot ................................................................................................................................... 40
Figure 13: V
Figure 14: Single-Ended Requirements for Differential Signals ........................................................................ 42
Figure 15: Definition of Differential AC-Swing and
Figure 16: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 45
Figure 17: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 46
Figure 18: ODT Levels and I-V Characteristics ................................................................................................ 47
Figure 19: ODT Timing Reference Load .......................................................................................................... 50
Figure 20:
Figure 21:
Figure 22:
Figure 23: Output Driver ................................................................................................................................ 53
Figure 24: DQ Output Signal .......................................................................................................................... 60
Figure 25: Differential Output Signal .............................................................................................................. 61
Figure 26: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 61
Figure 27: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 62
Figure 28: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 63
Figure 29: Nominal Slew Rate and
Figure 30: Nominal Slew Rate for
Figure 31: Tangent Line for
Figure 32: Tangent Line for
Figure 33: Nominal Slew Rate and
Figure 34: Nominal Slew Rate for
Figure 35: Tangent Line for
Figure 36: Tangent Line for
Figure 37: Refresh Mode ............................................................................................................................... 108
Figure 38: DLL Enable Mode to DLL Disable Mode ........................................................................................ 110
Figure 39: DLL Disable Mode to DLL Enable Mode ........................................................................................ 111
Figure 40: DLL Disable
Figure 41: Change Frequency During Precharge Power-Down ........................................................................ 114
Figure 42: Write Leveling Concept ................................................................................................................. 115
Figure 43: Write Leveling Sequence ............................................................................................................... 118
Figure 44: Write Leveling Exit Procedure ....................................................................................................... 119
Figure 45: Initialization Sequence ................................................................................................................. 121
Figure 46: MRS to MRS Command Timing (
Figure 47: MRS to nonMRS Command Timing (
Figure 48: Mode Register 0 (MR0) Definitions ................................................................................................ 124
Figure 49: READ Latency .............................................................................................................................. 126
Figure 50: Mode Register 1 (MR1) Definition ................................................................................................. 127
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
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AON and
AONPD and
ADC Definition ............................................................................................................................. 52
IX
for Differential Signals .............................................................................................................. 42
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AOF Definitions ............................................................................................................ 51
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DQSCK .................................................................................................................... 112
AOFPD Definitions ................................................................................................... 51
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IS (Command and Address – Clock) ..................................................................... 93
IH (Command and Address – Clock) ..................................................................... 94
DS (DQ – Strobe) ................................................................................................ 100
DH (DQ – Strobe) ............................................................................................... 101
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IH (Command and Address – Clock) ............................................................ 92
DH (DQ – Strobe) ....................................................................................... 99
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VAC for
VAC for
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IS (Command and Address – Clock) .............................................. 91
DS (DQ – Strobe) .......................................................................... 98
MRD) ......................................................................................... 122
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MOD) .................................................................................. 123
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DVAC ............................................................................... 43
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1Gb: x8, x16 Automotive DDR3 SDRAM
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