MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 163

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MT41J64M16JT-15E AIT:G

Manufacturer Part Number
MT41J64M16JT-15E AIT:G
Description
DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
Manufacturer
Micron
Datasheet
Figure 87: WRITE (BL8) to PRECHARGE
Figure 88: WRITE (BC4 Mode Register Setting) to PRECHARGE
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
Address
DQ BL8
DQ BC4
CK#
CK#
CK
CK
WRITE
WRITE
Valid
Valid
T0
T0
NOP
T1
NOP
T1
Notes:
Notes:
NOP
NOP
T2
T2
1. DI n = data-in from column n.
2. Seven subsequent elements of data-in are applied in the programmed order following
3. Shown for WL = 7 (AL = 0, CWL = 7).
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. The write recovery time (
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
NOP
T3
NOP
T3
WL = AL + CWL
WL = AL + CWL
DO n.
these times.
write data is shown at T7.
command can be issued to the same bank.
NOP
T4
NOP
T4
NOP
NOP
T5
T5
NOP
NOP
T6
T6
t
163
WR) is referenced from the first rising clock edge after the last
t
WR specifies the last burst WRITE cycle until the PRECHARGE
NOP
NOP
T7
T7
DI
n
DI
n
1Gb: x8, x16 Automotive DDR3 SDRAM
n + 1
n + 1
DI
DI
Micron Technology, Inc. reserves the right to change products or specifications without notice.
n + 2
NOP
n + 2
NOP
T8
DI
T8
DI
n + 3
n + 3
DI
DI
NOP
n + 4
NOP
T9
T9
DI
n + 5
DI
T10
NOP
n + 6
NOP
T10
DI
Indicates break
in time scale
Indicates break
in time scale
n + 7
DI
NOP
T11
NOP
T11
‹ 2010 Micron Technology, Inc. All rights reserved.
WRITE Operation
t
WR
Transitioning Data
Transitioning Data
NOP
NOP
T12
T12
t
WR
NOP
NOP
Ta0
Ta0
Don’t Care
Don’t Care
Valid
Valid
Ta1
Ta1
PRE
PRE

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