MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 87

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Command and Address Setup, Hold, and Derating
Table 53: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
t
t
t
t
t
IH(base,DC100)
IS(base,AC175)
IS(base,AC150)
IS(base,AC135)
IS(base,AC125)
Symbol
DDR3-800
200
350
275
–
–
The total
sheet
(page 68)) to the
(page 88)), respectively. Example:
transition, the input signal has to remain above/below V
t
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V
tion), a valid input signal is still required to complete the transition and to reach
V
fall between the values listed in Table 55 (page 88) and Table 58 (page 90), the derat-
ing values may be obtained by linear interpolation.
Setup (
last crossing of V
for a falling signal is defined as the slew rate between the last crossing of V
the first crossing of V
rate line between the shaded V
ing value (see Figure 29 (page 91)). If the actual signal is later than the nominal slew
rate line anywhere between the shaded V
line to the actual signal from the AC level to the DC level is used for derating value (see
Figure 31 (page 93)).
Hold (
last crossing of V
for a falling signal is defined as the slew rate between the last crossing of V
the first crossing of V
rate line between the shaded DC-to-V
ing value (see Figure 30 (page 92)). If the actual signal is earlier than the nominal slew
rate line anywhere between the shaded DC-to-V
line to the actual signal from the DC level to the V
(see Figure 32 (page 94)).
VAC (see Table 55 (page 88)).
IH(AC)
DDR3-1066
t
t
IS (base) and
/V
IH) nominal slew rate for a rising signal is defined as the slew rate between the
t
IS) nominal slew rate for a rising signal is defined as the slew rate between the
125
275
200
IL(AC)
–
–
t
IS (setup time) and
(see Figure 10 (page 39) for input signal requirements). For slew rates that
REF(DC)
IL(DC)max
t
DDR3-1333
IS and
Command and Address Setup, Hold, and Derating
t
IH (base) values (see Table 53; values come from Table 51
IL(AC)max
REF(DC)
190
140
65
–
–
and the first crossing of V
and the first crossing of V
t
. If the actual signal is always later than the nominal slew
IH derating values (see Table 54 (page 88) and Table 55
. If the actual signal is always earlier than the nominal slew
87
t
IH (hold time) required is calculated by adding the data
REF(DC)
DDR3-1600
t
1Gb: x8, x16 Automotive DDR3 SDRAM
IS (total setup time) =
IH(AC)
170
120
45
-to-AC region, use the nominal slew rate for derat-
REF(DC)
–
–
Micron Technology, Inc. reserves the right to change products or specifications without notice.
/V
REF(DC)
IL(AC)
region, use the nominal slew rate for derat-
DDR3-1866
-to-AC region, the slew rate of a tangent
REF(DC)
at the time of the rising clock transi-
IH(AC)min
REF(DC)
150
100
REF(DC)
65
–
–
region, the slew rate of a tangent
IH(AC)
t
level is used for derating value
IS (base) +
. Setup (
. Hold (
/V
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Unit
IL(AC)
ps
ps
ps
ps
ps
t
IH) nominal slew rate
t
IS) nominal slew rate
for some time
t
IS. For a valid
V
V
V
V
V
REF(DC)
IH(DC)min
Reference
IH(AC)
IH(AC)
IH(AC)
IH(AC)
IH(DC)
/V
/V
/V
/V
/V
and
IL(AC)
IL(AC)
IL(AC)
IL(AC)
IL(DC)
and