MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 151

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
DQS to DQ output timing is shown in Figure 73 (page 152). The DQ transitions between
valid data outputs must be within
also maintain a minimum HIGH and LOW time of
preamble, the DQ balls will either be floating or terminated, depending on the status of
the ODT signal.
Figure 74 (page 153) shows the strobe-to-clock timing during a READ. The crossing
point DQS, DQS# must transition within ±
out has no timing relationship to CK, only to DQS, as shown in Figure 74 (page 153).
Figure 74 (page 153) also shows the READ preamble and postamble. Typically, both
DQS and DQS# are High-Z to save power (V
DQS is driven LOW and DQS# is HIGH for
The READ postamble,
ing the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the
DQ is disabled or continues terminating, depending on the state of the ODT signal. Fig-
ure 79 (page 157) demonstrates how to measure
t
RPST, is one half clock from the last DQS, DQS# transition. Dur-
151
t
1Gb: x8, x16 Automotive DDR3 SDRAM
DQSQ of the crossing point of DQS, DQS#. DQS must
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
DQSCK of the clock crossing point. The data
RPRE. This is known as the READ preamble.
DDQ
). Prior to data output from the DRAM,
t
RPST.
t
QSH and
t
QSL. Prior to the READ
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READ Operation