MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 8

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MT41J64M16JT-15E AIT:G

Manufacturer Part Number
MT41J64M16JT-15E AIT:G
Description
DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
Manufacturer
Micron
Datasheet
1Gb: x8, x16 Automotive DDR3 SDRAM
Features
Figure 103: RESET Sequence ......................................................................................................................... 178
Figure 104: On-Die Termination ................................................................................................................... 179
Figure 105: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 184
Figure 106: Dynamic ODT: Without WRITE Command .................................................................................. 184
Figure 107: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 185
Figure 108: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 186
Figure 109: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 186
Figure 110: Synchronous ODT ...................................................................................................................... 188
Figure 111: Synchronous ODT (BC4) ............................................................................................................. 189
Figure 112: ODT During READs .................................................................................................................... 191
Figure 113: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 193
Figure 114: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 195
Figure 115: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 197
Figure 116: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 199
Figure 117: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 199
PDF: 09005aef84491df3
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1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN

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