MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 145

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

READ Operation
Figure 63: READ Latency
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
DQS, DQS#
Command
Address
CK#
DQ
CK
Bank a,
READ
Col n
T0
Notes:
CL = 8, AL = 0
READ bursts are initiated with a READ command. The starting column and bank ad-
dresses are provided with the READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive
latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-
ble in the mode register via the MRS command. Each subsequent data-out element is
valid nominally at the next positive or negative clock edge (that is, at the next crossing
of CK and CK#). Figure 63 shows an example of RL based on a CL setting of 8 and an AL
setting of 0.
DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on
DQS and HIGH state on DQS# is known as the READ preamble (
on DQS and the HIGH state on DQS#, coincident with the last data-out element, is
known as the READ postamble (
commands have been initiated, the DQ goes High-Z. A detailed explanation of
(valid data-out skew),
picted in Figure 74 (page 153). A detailed explanation of
to CK) is also depicted in Figure 74 (page 153).
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued
(page 147). If BC4 is enabled,
output, as shown in Figure 65 (page 147). Nonconsecutive READ data is reflected in
NOP
T7
1. DO n = data-out from column n.
2. Subsequent elements of data-out appear in the programmed order following DO n.
t
CCD cycles after the first READ command. This is shown for BL8 in Figure 64
NOP
T8
DO
n
t
QH (data-out window hold), and the valid data window are de-
NOP
T9
145
t
CCD must still be met, which will cause a gap in the data
t
RPST). Upon completion of a burst, assuming no other
1Gb: x8, x16 Automotive DDR3 SDRAM
NOP
T10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Indicates break
in time scale
NOP
T11
t
DQSCK (DQS transition skew
Transitioning Data
‹ 2010 Micron Technology, Inc. All rights reserved.
T12
NOP
t
RPRE). The LOW state
READ Operation
NOP
T12
Don’t Care
t
DQSQ