MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 126

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Precharge Power-Down (Precharge PD)
CAS Latency (CL)
Figure 49: READ Latency
DQS, DQS#
DQS, DQS#
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Command
Command
CK#
CK#
DQ
DQ
CK
CK
READ
READ
T0
T0
Notes:
NOP
NOP
T1
T1
quired to program the correct value of write recovery and is calculated by dividing
(ns) by
roundup (
The precharge PD bit applies only when precharge power-down mode is being used.
When MR0[12] is set to 0, the DLL is off during precharge power-down providing a low-
er standby current mode; however,
MR0[12] is set to 1, the DLL continues to run during precharge power-down mode to
enable a faster exit of precharge power-down mode; however,
when exiting (see Power-Down Mode (page 169)).
The CL is defined by MR0[6:4], as shown in Figure 48 (page 124). CAS latency is the de-
lay, in clock cycles, between the internal READ command and the availability of the first
bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not support
half-clock latencies.
Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis-
tered at clock edge n, and the CAS latency is m clocks, the data will be available nomi-
nally coincident with clock edge n + m. on page through Table 48 (page 65) indicate the
CLs supported at various operating frequencies.
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal
t
CK (ns) and rounding up a noninteger value to the next integer: WR (cycles) =
NOP
NOP
T2
T2
t
WR [ns]/
AL = 0, CL = 6
t
NOP
NOP
T3
T3
CK [ns]).
t
DQSCK and nominal
AL = 0, CL = 8
126
NOP
NOP
T4
T4
1Gb: x8, x16 Automotive DDR3 SDRAM
t
XPDLL must be satisfied when exiting. When
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
NOP
T5
T5
t
DSDQ.
NOP
NOP
T6
T6
Mode Register 0 (MR0)
DI
n
t
‹ 2010 Micron Technology, Inc. All rights reserved.
XP must be satisfied
n + 1
Transitioning Data
DI
NOP
NOP
T7
T7
n + 2
DI
n + 3
DI
NOP
NOP
T8
T8
Don’t Care
n + 4
DI
DI
n
t
WR