MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 196

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins
t
istered HIGH.
transition period is
ODT assertion during power-down exit results in an R
t
(MAX) and ODTLon ×
may result in an R
t
Table 86 (page 195) summarizes these parameters.
If AL has a large value, the uncertainty of the R
cause ODTLon and ODTLoff are derived from WL, and WL is equal to CWL + AL. Fig-
ure 115 (page 197) shows three different cases:
• ODT C: Asynchronous behavior before
• ODT B: ODT state changes during the transition period, with
• ODT A: ODT state changes after the transition period with synchronous response.
ANPD prior to CKE first being registered HIGH, and ends
AONPD (MIN) and ODTLon ×
AOF (MIN), or as late as the greater of
off ×
Asynchronous to Synchronous ODT Mode Transition (Power-
t
CK +
t
AOF (MIN), and ODTLoff ×
t
ANPD is equal to the greater of ODTLoff + 1
TT
t
ANPD +
change as early as the lesser of
t
CK +
t
t
AON (MAX). ODT de-assertion during power-down exit
196
XPDLL.
t
CK +
t
AON (MIN), or as late as the greater of
t
AOFPD (MAX) and ODTLoff ×
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t
t
CK +
ANPD.
TT
t
AOF (MAX) >
state becomes quite large. This is be-
t
AOFPD (MIN) and ODTLoff ×
TT
change as early as the lesser of
t
t
XPDLL after CKE is first reg-
CK or ODTLon + 1
t
AOFPD (MAX).
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t
AOFPD (MIN) < ODTL-
t
CK +
Down Exit)
t
t
AOF (MAX).
AONPD
t
CK. The
t
CK +