MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 167

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 91: Self Refresh Entry/Exit Timing
Command
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
RESET#
Address
ODT
CK#
CKE
CK
2
2
T0
NOP
t
RP
8
Enter self refresh mode
(synchronous)
SRE (REF)
t
t
IS
IS
Notes:
T1
3
t
CPDED
1. The clock must be valid and stable, meeting
2. ODT must be disabled and R
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6.
7.
8. The device must be in the all banks idle state prior to entering self refresh mode. For
9. Self refresh exit is asynchronous; however,
t
CKSRE
NOP
T2
tering self refresh mode, and at least
clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and
unchanged from entry and during self refresh mode, then
apply; however,
R
inputs becoming “Don’t Care.”
t
t
example, all banks must be precharged,
progress.
clock edge where CKE HIGH satisfies
t
XS is required before any commands not requiring a locked DLL.
XSDLL is required before any commands requiring a locked DLL.
ISXR is satisfied at Tc1.
4
TT,nom
1
and R
Ta0
TT(WR)
t
CKESR (MIN)
t
CKESR must be satisfied prior to exiting at SRX.
are disabled in the mode registers, ODT can be a “Don’t Care.”
1
167
Tb0
TT
off prior to entering self refresh at state T1. If both
1Gb: x8, x16 Automotive DDR3 SDRAM
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CKSRX
t
ISXR at Tc1.
t
Tc0
CKSRX prior to exiting self refresh mode, if the
t
IH
t
1
RP must be met, and no data bursts can be in
t
XS and
Exit self refresh mode
t
SRX (NOP)
CK specifications at least
(asynchronous)
t
IS
Tc1
t
CKSRX timing is also measured so that
t
XSDLL timings start at the first rising
SELF REFRESH Operation
t
NOP
t
CKSRE and
XS
Td0
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6, 9
5
Indicates break
in time scale
t
Valid
Valid
Valid
t
CKSRE after en-
Te0
CKSRX do not
6
Valid
Don’t Care
Valid
Valid
Valid
Tf0
7