MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 14

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Functional Block Diagrams
Figure 3: 128 Meg x 8 Functional Block Diagram
RZQ
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
V
SSQ
A[13:0]
BA[2:0]
ZQ
CK, CK#
RESET#
RAS#
CAS#
ODT
WE#
CKE
A12
CS#
17
Address
register
Mode registers
Control
logic
16
14
Refresh
counter
ZQCL, ZQCS
10
3
BC4 (burst chop)
OTF
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
14
address
3
Row-
MUX
Column-
counter/
address
control
14
Bank
logic
latch
ZQ CAL
decoder
address
Bank 0
latch
row-
and
Bank 1
Bank 2
7
3
Bank 3
Bank 4
16,384
Bank 5
Bank 6
Columns 0, 1, and 2
Bank 7
To ODT/output drivers
(16,384 x 128 x 64)
Sense amplifiers
DM mask logic
I/O gating
decoder
memory
Column
Bank 0
array
8,192
(128
x64)
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
14
Bank 6
Bank 7
1Gb: x8, x16 Automotive DDR3 SDRAM
64
BC4
OTF
Micron Technology, Inc. reserves the right to change products or specifications without notice.
64
64
Columns 0, 1, and 2
interface
READ
CK, CK#
MUX
FIFO
data
and
Data
Data
8
8
lower nibble for BC4)
Functional Block Diagrams
(select upper or
Column 2
drivers
WRITE
input
logic
and
control
ODT
CK, CK#
drivers
READ
DLL
BC4
‹ 2010 Micron Technology, Inc. All rights reserved.
DQ[7:0]
DQS, DQS#
sw1
sw1
sw1
R
R
R
V
V
TT,nom
TT,nom
V
TT,nom
DDQ
DDQ
DDQ
/2
/2
/2
DQ8
R
R
R
sw2
sw2
TT(WR)
sw2
TT(WR)
TT(WR)
(1 . . . 8)
(1, 2)
DQ[7:0]
DQS, DQS#
DM/TDQS
(shared pin)
TDQS#