MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 132

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MC9S12P64VQK

Manufacturer Part Number
MC9S12P64VQK
Description
16-bit Microcontrollers - MCU 16 BIT 64K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12P64VQK

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
64 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to 105 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Interface Type
I2C, SCI, SPI
Program Memory Type
Flash

Available stocks

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Manufacturer
Quantity
Price
Part Number:
MC9S12P64VQK
Manufacturer:
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Quantity:
10 000
Background Debug Module (S12SBDMV1)
5.1.1
The BDM includes these distinctive features:
5.1.2
BDM is available in all operating modes but must be enabled before firmware commands are executed.
Some systems may have a control bit that allows suspending the function during background debug mode.
5.1.2.1
All of these operations refer to the part in run mode and not being secured. The BDM does not provide
controls to conserve power during run mode.
5.1.2.2
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run
mode operation. Secure operation prevents access to Flash other than allowing erasure. For more
information please see
132
Single-wire communication with host development system
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
GO_UNTIL command
Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 firmware commands execute from the standard BDM firmware lookup table
Software control of BDM operation during wait mode
When secured, hardware commands are allowed to access the register space in special single chip
mode, if the Flash erase tests fail.
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
BDM hardware commands are operational until system stop mode is entered
Normal modes
General operation of the BDM is available and operates the same in all normal modes.
Special single chip mode
In special single chip mode, background operation is enabled and active out of reset. This allows
programming a system with blank memory.
Features
Modes of Operation
Regular Run Modes
Secure Mode Operation
Section 5.4.1,
S12P-Family Reference Manual, Rev. 1.13
“Security”.
Freescale Semiconductor

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