MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 229
MC9S12P64VQK
Manufacturer Part Number
MC9S12P64VQK
Description
16-bit Microcontrollers - MCU 16 BIT 64K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of MC9S12P64VQK
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
64 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to 105 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Interface Type
I2C, SCI, SPI
Program Memory Type
Flash
Available stocks
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7.3.2.19
The CPMUHTTR register configures the trimming of the S12CPMU temperature sense.
Read: Anytime
Write: Anytime
Freescale Semiconductor
0x02F7
HTTR[3:0]
After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for
Reset
HTOE
Field
details.
3–0
7
W
R
HTOE
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
High Temperature Trimming Register (CPMUHTTR)
High Temperature Trimming Bits — See
0
7
= Unimplemented or Reserved
HTTR[3]
HTTR[2]
HTTR[1]
HTTR[0]
0
0
6
Bit
S12P-Family Reference Manual, Rev. 1.13
Increases V
Increases V
Increases V
Increases V
0
0
5
HT
HT
HT
HT
twice of HTTR[2]
twice of HTTR[1]
twice of HTTR[0]
(to compensate Temperature Offset)
Table 1-27
0
0
4
Trimming Effect
Description
for trimming effects.
S12 Clock, Reset and Power Management Unit (S12CPMU)
HTTR3
F
3
HTTR2
F
2
HTTR1
F
1
HTTR0
F
0
229
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