MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 370

• Manufacturer Part Number: MC9S12P64VQK
• Description: 16-bit Microcontrollers - MCU 16 BIT 64K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12P64VQK

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 64 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to 105 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT
• Interface Type: I2C, SCI, SPI
• Program Memory Type: Flash

Serial Communication Interface (S12SCIV5)
11.3.2.3
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
11.3.2.4
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
370
Module Base + 0x0000
Module Base + 0x0001
RXEDGIF
BERRIF
BERRV
Reset
Reset
BKDIF
Field
7
2
1
0
W
W
R
R
RXEDGIE
RXEDGIF
Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,
rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active receive on the receive input has occurred
1 An active edge on the receive input has occurred
Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and
a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value
sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is
received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing
a “1” to it.
0 No break signal was received
1 A break signal was received
SCI Alternative Status Register 1 (SCIASR1)
SCI Alternative Control Register 1 (SCIACR1)
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 11-7. SCI Alternative Control Register 1 (SCIACR1)
Figure 11-6. SCI Alternative Status Register 1 (SCIASR1)
0
0
0
0
6
6
Table 11-6. SCIASR1 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
0
0
0
0
5
5
0
0
0
0
4
4
Description
0
0
0
0
3
3
BERRV
0
0
0
2
2
BERRIE
BERRIF
Freescale Semiconductor
0
0
1
1
BKDIE
BKDIF
0
0
0
0