MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 83

• Manufacturer Part Number: MC9S12P64VQK
• Description: 16-bit Microcontrollers - MCU 16 BIT 64K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12P64VQK

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 64 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to 105 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT
• Interface Type: I2C, SCI, SPI
• Program Memory Type: Flash

1. Read: Anytime
2.3.34
Freescale Semiconductor
Address 0x0252
Write: Anytime
DDRM
DDRM
DDRM
PTIM
Field
Field
Reset
5-0
5
4
3
W
R
Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M Data Direction Register (DDRM)
0
0
7
0
0
6
Figure 2-32. Port M Data Direction Register (DDRM)
Table 2-30. DDRM Register Field Descriptions
Table 2-29. PTIM Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
DDRM5
5
0
DDRM4
0
4
Description
Description
DDRM3
0
3
DDRM2
0
2
Port Integration Module (S12PPIMV1)
Access: User read/write
DDRM1
0
1
DDRM0
0
0
83
(1)