MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 473

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MC9S12P64VQK

Manufacturer Part Number
MC9S12P64VQK
Description
16-bit Microcontrollers - MCU 16 BIT 64K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12P64VQK

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
64 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to 105 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Interface Type
I2C, SCI, SPI
Program Memory Type
Flash

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12P64VQK
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 14
Timer Module (TIM16B8CV2) Block Description
14.1
The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable
prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from microseconds to many seconds.
This timer contains 8 complete input capture/output compare channels and one pulse accumulator. The
input capture function is used to detect a selected transition edge and record the time. The output compare
function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator
Freescale Semiconductor
Revision
Number
V02.04
V02.05
V02.06
Introduction
Revision Date
26 Aug 2009
1 Jul 2008
9 Jul 2009
14.3.2.2/14-480
14.3.2.3/14-481
14.3.2.4/14-482
14.4.2/14-497
14.4.3/14-497
14.4.2/14-497
14.4.3/14-497
14.1.2/14-474
14.4.3/14-497
14.3.2.12/14-
14.3.2.13/14-
14.3.2.16/14-
14.3.2.12/14-
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14.3.2.15/14-
14.3.2.16/14-
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Sections
Affected
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S12P-Family Reference Manual, Rev. 1.13
Table 14-1. Revision History
- Revised flag clearing procedure, whereby TEN bit must be set when clearing
flags.
- Revised flag clearing procedure, whereby TEN or PAEN bit must be set
when clearing flags.
- Add fomula to describe prescaler
- Correct typo: TSCR ->TSCR1
- Correct reference: Figure 1-25 -> Figure 1-31
- Add description, “a counter overflow when TTOV[7] is set”, to be the
condition of channel 7 override event.
- Phrase the description of OC7M to make it more explicit
Description of Changes
473

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