MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 74

• Manufacturer Part Number: MC9S12P64VQK
• Description: 16-bit Microcontrollers - MCU 16 BIT 64K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12P64VQK

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 64 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to 105 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT
• Interface Type: I2C, SCI, SPI
• Program Memory Type: Flash

1. Read: Anytime
1. Read: Anytime
Port Integration Module (S12PPIMV1)
2.3.19
2.3.20
74
Address 0x0243
Address 0x0244
Write: Anytime
Write: Anytime
RDRT
PERT
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port T reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port T pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
RDRT7
PERT7
Port T Reduced Drive Register (RDRT)
Port T Pull Device Enable Register (PERT)
0
0
7
7
RDRT6
PERT6
Figure 2-18. Port T Pull Device Enable Register (PERT)
0
0
6
6
Figure 2-17. Port T Reduced Drive Register (RDRT)
Table 2-17. RDRT Register Field Descriptions
Table 2-18. PERT Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
RDRT5
PERT5
5
0
5
0
RDRT4
PERT4
0
0
4
4
Description
Description
RDRT3
PERT3
0
0
3
3
RDRT2
PERT2
0
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
RDRT1
PERT1
0
0
1
1
RDRT0
PERT0
0
0
0
0
(1)
(1)