MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 337

• Manufacturer Part Number: MC9S12P64VQK
• Description: 16-bit Microcontrollers - MCU 16 BIT 64K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12P64VQK

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 64 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to 105 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT
• Interface Type: I2C, SCI, SPI
• Program Memory Type: Flash

10.3.2.3
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
Read: anytime
Write: anytime
Freescale Semiconductor
Module Base + 0x0002
PPOL3
PPOL2
PPOL1
PPOL0
Reset
Field
3
2
1
0
W
R
Pulse Width Channel 3 Polarity
0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 2 Polarity
0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 1 Polarity
0 PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 0 Polarity
0 PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached.
PWM Clock Select Register (PWMCLK)
0
0
7
Register bits PCLK0 to PCLK5 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
= Unimplemented or Reserved
0
0
6
Table 10-3. PWMPOL Field Descriptions (continued)
Figure 10-5. PWM Clock Select Register (PWMCLK)
S12P-Family Reference Manual, Rev. 1.13
PCLK5
0
5
PCLK4
NOTE
0
4
Description
PCLK3
Pulse-Width Modulator (PWM8B6CV1) Block Description
0
3
PCLK2
0
2
PCLK1
0
1
PCLK0
0
0
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