MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 351

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MC9S12P64VQK

Manufacturer Part Number
MC9S12P64VQK
Description
16-bit Microcontrollers - MCU 16 BIT 64K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12P64VQK

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
64 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to 105 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Interface Type
I2C, SCI, SPI
Program Memory Type
Flash

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12P64VQK
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Read: anytime
Write: anytime
10.3.2.15 PWM Shutdown Register (PWMSDN)
The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency
cases.
Read: anytime
Write: anytime
Freescale Semiconductor
Module Base + 0x001D
Module Base + 0x00E
PWMRSTRT
PWMLVL
PWMIE
PWMIF
Reset
Reset
Field
7
6
5
4
W
W
R
R
PWMIF
PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will be
flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect.
0 No change on PWM5IN input.
1 Change on PWM5IN input
PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.
0 PWM interrupt is disabled.
1 PWM interrupt is enabled.
PWM Restart — The PWM can only be restarted if the PWM channel input 5 is deasserted. After writing a logic 1
to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes
next “counter = 0” phase.
Also, if the PWM5ENA bit is reset to 0, the PWM do not start before the counter passes 0x0000.
The bit is always read as 0.
PWM Shutdown Output Level — If active level as defined by the PWM5IN input, gets asserted all enabled PWM
channels are immediately driven to the level defined by PWMLVL.
0 PWM outputs are forced to 0
1 PWM outputs are forced to 1.
Bit 7
1
0
7
7
= Unimplemented or Reserved
PWMIE
Figure 10-32. PWM Channel Duty Registers (PWMDTY5)
6
1
0
6
6
Figure 10-33. PWM Shutdown Register (PWMSDN)
Table 10-10. PWMSDN Field Descriptions
PWMRSTRT
S12P-Family Reference Manual, Rev. 1.13
5
1
0
0
5
5
PWMLVL
4
1
0
4
4
Description
Pulse-Width Modulator (PWM8B6CV1) Block Description
3
1
0
0
3
3
PWM5IN
2
1
0
2
2
PWM5INL
1
1
0
1
1
PWM5ENA
Bit 0
1
0
0
0
351

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