S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 187
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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5
6
2.4.2
The following tables show the individual register maps of groups
G3 (Table
2.4.2.1
Freescale Semiconductor
Preset by factory.
Routing register only available on G(A)240 and G(A)192 only. Takes only effect if the PKGCR is set to 100 LQFP.
Global Address
Register Name
PORTC
PORTD
PORTB
PORTE
0x0000
PORTA
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
DDRA
DDRB
DDRC
DDRD
DDRE
2-21).
Register Map
Block Register Map (G1)
To maintain SW compatibility write data to unimplemented register bits
must be zero.
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
DDRC7
DDRD7
DDRA7
DDRB7
Bit 7
PB7
PC7
PD7
PA7
0
0
MC9S12G Family Reference Manual, Rev.1.23
= Unimplemented or Reserved
DDRC6
DDRD6
DDRA6
DDRB6
Table 2-19. Block Register Map (G1)
PB6
PC6
PD6
PA6
6
0
0
DDRA5
DDRB5
DDRC5
DDRD5
PC5
PD5
PB5
PA5
5
0
0
NOTE
DDRA4
DDRB4
DDRC4
DDRD4
PC4
PD4
PA4
PB4
4
0
0
G1 (Table
DDRA3
DDRB3
DDRC3
DDRD3
PB3
PC3
PD3
PA3
3
0
0
Port Integration Module (S12GPIMV1)
DDRC2
DDRD2
DDRA2
DDRB2
2-19),
PB2
PC2
PD2
PA2
2
0
0
G2 (Table
DDRC1
DDRD1
DDRA1
DDRB1
DDRE1
PB1
PC1
PD1
PE1
PA1
1
2-20) and
DDRA0
DDRB0
DDRC0
DDRD0
DDRE0
Bit 0
PC0
PD0
PB0
PE0
PA0
189
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