S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 359
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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Chapter 10
S12 Clock, Reset and Power Management Unit (S12CPMU)
Revision History
10.1
This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU).
10.1.1
The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
Freescale Semiconductor
Number
Version
V04.10
V04.11
V04.12
•
•
•
•
•
•
•
•
The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock
source. It is designed for optimal start-up margin with typical quartz crystals and ceramic
resonators.
The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required
chip internal voltages and voltage monitors.
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
The Internal Reference Clock (IRC1M) provides a1MHz clock.
Supports quartz crystals or ceramic resonators from 4MHz to 16MHz.
High noise immunity due to input hysteresis and spike filtering.
Low RF emissions with peak-to-peak swing limited dynamically
Transconductance (gm) sized for optimum start-up margin for typical crystals
27 April 12 27 April 12
Revision
23 Aug 10
Introduction
01 Jul 10
Date
Features
Effective
23 Aug 10
01 Jul 10
Date
MC9S12G Family Reference Manual, Rev.1.23
Author
Added TC trimming to feature list
Removed feature of adaptive oscillator filter. Register bits 6 and 4to
0in the CPMUOSC register are marked reserved and do not alter.
Corrected wording for API interrupt flag
Changed notation of IRC trim values for 0x00000 to 0b00000
Description of Changes
361
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