S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 212
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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1
1
Port Integration Module (S12GPIMV1)
2.4.3.14
214
Address 0x001F
IRQEN
Read: Anytime
Write: Only in special mode
Read: Anytime
Write:
IRQE
Field
Reset
7
6
IRQE: Once in normal mode, anytime in special mode
IRQEN: Anytime
W
R
Reserved
IRQ select edge sensitive only—
1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when
0 IRQ pin configured for low level recognition
IRQ enable—
1 IRQ pin is connected to interrupt logic
0 IRQ pin is disconnected from interrupt logic
IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
Reserved Register
7
x
These reserved registers are designed for factory test purposes only and are
not intended for general user access. Writing to these registers when in
special mode can alter the module’s functionality.
If the input is driven to active level (IRQ=0) a write access to set either
IRQCR[IRQEN] and IRQCR[IRQE] to 1 simultaneously or to set
IRQCR[IRQEN] to 1 when IRQCR[IRQE]=1 causes an IRQ interrupt to be
generated if the I-bit is cleared. Refer to
edge-sensitive
Reserved
x
6
Table 2-34. IRQCR Register Field Descriptions
mode”.
MC9S12G Family Reference Manual,
Reserved
Figure 2-15. Reserved Register
x
5
Reserved
NOTE
x
4
Description
Section 2.6.3, “Enabling IRQ
Reserved
3
x
Rev.1.23
Reserved
2
x
Reserved
Freescale Semiconductor
Access: User read/write
1
x
Reserved
0
x
1
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