S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 545
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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Chapter 16
Analog-to-Digital Converter (ADC12B16CV2)
Revision History
Freescale Semiconductor
Number
Version
V02.00
V02.01
V02.03
V02.04
V02.05
V02.06
V02.08
V02.09
V02.10
V02.11
V02.12
v02.07
18 June 2009 18 June 2009
22. Jun 2012
29. Jun 2012
09 Feb 2010
26 Feb 2010
26 Mar 2010
25 Aug 2010
09 Sep 2010
11 Feb 2011
29 Mar 2011
14 Apr 2010
02 Oct 2012
Revision
Date
22. Jun 2012
29. Jun 2012
09 Feb 2010
26 Feb 2010
16 Mar 2010
25 Aug 2010
09 Sep 2010
11 Feb 2011
29 Mar 2011
14 Apr 2010
02 Oct 2012
Effective
Date
MC9S12G Family Reference Manual, Rev.1.23
Author
Initial version copied 12 channel block guide
Updated
description of internal channels.
Updated register ATDDR (left/right justified result) description
in section
added
Fixed typo in
resolution
Corrected
description of internal channels.
Corrected typo: Reset value of ATDDIEN register
Corrected typos to be in-line with SoC level pin naming
conventions for VDDA, VSSA, VRL and VRH.
Removed feature of conversion during STOP and general
wording clean up done in
Description
Update of internal only information.
Connectivity Information regarding internal channel_6 added
to
Fixed typo in bit description field
CB, CA. Last sentence contained a wrong highest channel
number (it is not AN7 to AN0 instead it is AN15 to AN0).
Updated register wirte access information in section
16.3.2.9/16-566
Removed IP name in block diagram
Added user information to avoid maybe false external trigger
events when enabling the external trigger mode
(Section 16.4.2.1, “External Trigger
Table
Table 16-21
16-15.
Table 16-15
16.3.2.12.1/16-568
Table 16-15
Table 16-9
Description of Changes
to improve feature description.
Analog Input Channel Select Coding -
Analog Input Channel Select Coding -
- conversion result for 3mV and 10bit
Section 16.4, “Functional
and
Table 16-14
16.3.2.12.2/16-569
Input).
Figure 16-1
for bits CD, CC,
and
547
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