S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 713
S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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Freescale Semiconductor
SPTEF
MODF
Field
5
4
1
2
1
2
XFRW Bit
XFRW Bit
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 21.3.2.2, “SPI Control Register 2
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Data in SPIDRH is lost in this case.
SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read
of SPIDRL after reading SPISR with SPIF == 1.
Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.
Data in SPIDRH is undefined in this case.
0
1
0
1
Read SPISR with SPTEF == 1 then
Read SPISR with SPTEF == 1
Read SPISR with SPIF == 1
Read SPISR with SPIF == 1
Table 21-9. SPTEF Interrupt Flag Clearing Sequence
Table 21-8. SPIF Interrupt Flag Clearing Sequence
MC9S12G Family Reference Manual, Rev.1.23
Table 21-7. SPISR Field Descriptions
SPTEF Interrupt Flag Clearing Sequence
SPIF Interrupt Flag Clearing Sequence
(SPICR2)”. The flag is cleared automatically by a read of the SPI status
then
then
then
Byte Write to SPIDRH
Description
Byte Read SPIDRH
Word Write to (SPIDRH:SPIDRL)
Word Read (SPIDRH:SPIDRL)
Byte Write to SPIDRL
Byte Read SPIDRL
Write to SPIDRL
Read SPIDRL
13
or
or
2
or
or
Byte Write to SPIDRL
Serial Peripheral Interface (S12SPIV5)
Byte Read SPIDRL
1
12
1
1
1
Table
21-9.
715
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