S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 471
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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13.2
This section lists all inputs to the ADC10B12C block.
13.2.1
13.2.1.1
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
13.2.1.2
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connectivity of these inputs!
13.2.1.3
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
13.2.1.4
These pins are the power supplies for the analog circuitry of the ADC10B12C block.
13.3
This section provides a detailed description of all registers accessible in the ADC10B12C.
13.3.1
Figure 13-2
Freescale Semiconductor
Address
0x0000
0x0001
0x0002
Signal Description
Memory Map and Register Definition
ATDCTL0
ATDCTL1
ATDCTL2
Detailed Signal Descriptions
Module Memory Map
Name
gives an overview on all ADC10B12C registers.
ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
ETRIG3, ETRIG2, ETRIG1, ETRIG0
VRH, VRL
VDDA, VSSA
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
W
W
W
R
R
R
Figure 13-2. ADC10B12C Register Summary (Sheet 1 of 3)
ETRIGSEL
Reserved
Bit 7
0
MC9S12G Family Reference Manual, Rev.1.23
= Unimplemented or Reserved
SRES1
AFFC
6
0
Reserved ETRIGLE
SRES0
5
0
NOTE
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
4
0
ETRIGP
WRAP3
3
Analog-to-Digital Converter (ADC10B12CV2)
ETRIGE
WRAP2
2
WRAP1
ASCIE
1
ACMPIE
WRAP0
Bit 0
473
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