S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 605
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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1
Module Base + 0x0018 to Module Base + 0x001B
1
Module Base + 0x0010 to Module Base + 0x0013
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
18.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Freescale Semiconductor
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
AC[7:0]
AC[7:0]
Field
Field
7-0
7-0
Figure 18-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Figure 18-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Reset
Reset
W
R
W
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
AC7
AC7
0
7
0
7
Table 18-22. CANIDAR0–CANIDAR3 Register Field Descriptions
Table 18-23. CANIDAR4–CANIDAR7 Register Field Descriptions
AC6
AC6
0
6
0
6
MC9S12G Family Reference Manual, Rev.1.23
AC5
AC5
0
5
5
0
AC4
AC4
0
4
Description
Description
0
4
Freescale’s Scalable Controller Area Network (S12MSCANV3)
AC3
AC3
0
3
3
0
AC2
AC2
0
2
0
2
Access: User read/write
Access: User read/write
AC1
AC1
0
1
1
0
AC0
AC0
0
0
0
0
607
1
1
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