S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 889
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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26.3.2.2
The FSEC register holds all bits associated with the security of the MCU and Flash module.
1
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see
indicated by reset condition F in
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set
to leave the Flash module in a secured state with backdoor key access disabled.
Freescale Semiconductor
KEYEN[1:0]
Loaded from IFR Flash configuration field, during reset sequence.
RNV[5:2]
SEC[1:0]
Offset Module Base + 0x0001
Reset
Field
7–6
5–2
1–0
W
R
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
Flash module as shown in
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in
Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Flash Security Register (FSEC)
F
7
1
KEYEN[1:0]
F
= Unimplemented or Reserved
6
1
1
Preferred KEYEN state to disable backdoor key access.
KEYEN[1:0]
Figure 26-6. Flash Security Register (FSEC)
MC9S12G Family Reference Manual, Rev.1.23
00
01
10
11
Figure
Table
Table 26-9. FSEC Field Descriptions
Table 26-10. Flash KEYEN States
F
5
1
26-10.
26-6. If a double bit fault is detected while reading the P-Flash
Status of Backdoor Key Access
F
4
1
RNV[5:2]
Description
DISABLED
DISABLED
DISABLED
ENABLED
F
3
1
1
48 KByte Flash Module (S12FTMRG48K1V1)
F
2
1
F
Table
1
1
Table
SEC[1:0]
26-4) as
26-11. If the
F
0
1
891
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