S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 305
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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Since the host knows the target serial clock frequency, the SYNC command (used to abort a command)
does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC
very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to
assure the SYNC pulse will not be misinterpreted by the target. See
Timed Reference
Figure 7-12
command. Note that, after the command is aborted a new command could be issued by the host computer.
Figure 7-13
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not
a probable situation, the protocol does not prevent this conflict from happening.
Freescale Semiconductor
(Target MCU)
Drives SYNC
To BKGD Pin
BKGD Pin
Target MCU
BDM Clock
BKGD Pin
BKGD Pin
Drives to
Host
shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE
shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
READ_BYTE
Figure 7-12
Pulse”.
the READ_BYTE Command
READ_BYTE CMD is Aborted
Host
Figure 7-12. ACK Abort Procedure at the Command Level
and Starts to Execute
Figure 7-13. ACK Pulse and SYNC Request Conflict
does not represent the signals in a true timing scale
by the SYNC Request
Memory Address
Target
Host SYNC Request Pulse
BDM Decode
MC9S12G Family Reference Manual, Rev.1.23
(Out of Scale)
ACK Pulse
16 Cycles
Host and
Target Drive
to BKGD Pin
At Least 128 Cycles
NOTE
Electrical Conflict
High-Impedance
READ_STATUS
Host
SYNC Response
From the Target
(Out of Scale)
Target
New BDM Command
Section 7.4.9, “SYNC — Request
Background Debug Module (S12SBDMV1)
New BDM Command
Host
Speedup Pulse
Target
307
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