S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 766
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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Timer Module (TIM16B8CV3)
23.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
Read: Any time
Write: Any time
When PAEN is set, the Pulse Accumulator counter is enabled. The Pulse Accumulator counter shares the
input pin with IOC7.
768
Module Base + 0x0020
CLK[1:0]
PAMOD
PEDGE
Reset
PAOVI
PAEN
Field
PAI
3:2
6
5
4
1
0
W
R
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table
0 Event counter mode.
1 Gated time accumulation mode.
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See
0 Falling edges on IOC7 pin cause the count to be increased.
1 Rising edges on IOC7 pin cause the count to be increased.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
Clock Select Bits — Refer to
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
0
0
7
edge on IOC7 sets the PAIF flag.
on IOC7 sets the PAIF flag.
23-19.
Figure 23-24. 16-Bit Pulse Accumulator Control Register (PACTL)
Unimplemented or Reserved
PAEN
0
6
MC9S12G Family Reference Manual,
Table 23-18. PACTL Field Descriptions
PAMOD
Table
0
5
23-20.
PEDGE
0
4
Table
Description
23-19.
CLK1
0
3
Rev.1.23
CLK0
0
2
Freescale Semiconductor
PAOVI
0
1
PAI
0
0
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