S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 211
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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2.4.3.12
2.4.3.13
Freescale Semiconductor
Address 0x001E
Read: Anytime
Write: Anytime
NCLKX2
Reset:
Address 0x001C
NECLK
DIV16
Field
EDIV
Reset
4-0
7
6
5
W
R
W
R
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
NECLK
IRQE
ECLK Control Register (ECLKCTL)
IRQ Control Register (IRQCR)
0
7
1
7
IRQEN
NCLKX2
0
6
1
6
Table 2-33. ECLKCTL Register Field Descriptions
Figure 2-13. ECLK Control Register (ECLKCTL)
Figure 2-14. IRQ Control Register (IRQCR)
MC9S12G Family Reference Manual, Rev.1.23
DIV16
0
0
5
0
5
EDIV4
0
0
4
0
4
Description
EDIV3
3
0
0
3
0
EDIV2
0
0
2
0
2
Port Integration Module (S12GPIMV1)
Access: User read/write
Access: User read/write
EDIV1
0
0
1
0
1
EDIV0
0
0
0
0
0
213
1
1
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