S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 105

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

2.4.4
Ports P and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
Freescale Semiconductor
2-60).
Pin interrupts
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
1. These values include the spread of the oscillator frequency over temperature,
voltage and process.
Uncertain
Figure 2-65. Interrupt Glitch Filter on Port P and J (PPS=0)
Ignored
Pulse
Valid
S12P-Family Reference Manual, Rev. 1.13
t
Table 2-60. Pulse Detection Criteria
pign
t
pval
3 < t
(Figure
t
t
pulse
pulse
pulse
STOP
uncertain
< 4
≤ 3
≥ 4
2-66) shorter than a specified time from generating an
bus clocks
bus clocks
bus clocks
Unit
Mode
t
pign
STOP
< t
t
t
pulse
pulse
pulse
Port Integration Module (S12PPIMV1)
(1)
≤ t
< t
≥ t
pign
pval
pval
(Figure 2-65
and
105