S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 301

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

8.4.5.7
The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving,
however the register map can still be accessed as specified.
8.4.5.8
The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity
is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0). The sensitivity to existing
CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line (see
control bit WUPM in
This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines.
Such glitches can result from—for example—electromagnetic interference within noisy environments.
8.4.6
The reset state of each individual bit is listed in
the registers and their bit-fields.
8.4.7
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated
flags. Each interrupt is listed and described separately.
8.4.7.1
The MSCAN supports four interrupt vectors (see
(for details see
Section 8.3.2.8, “MSCAN Transmitter Interrupt Enable Register
8.4.7.2
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
Freescale Semiconductor
Reset Initialization
Interrupts
Wake-Up Interrupt (WUPIF)
Error Interrupts Interrupt (CSCIF, OVRIF)
Receive Interrupt (RXF)
Transmit Interrupts (TXE[2:0])
Disabled Mode
Programmable Wake-Up Function
Description of Interrupt Operation
Transmit Interrupt
The dedicated interrupt vector addresses are defined in the
Interrupts
Section 8.3.2.6, “MSCAN Receiver Interrupt Enable Register
Section 8.3.2.2, “MSCAN Control Register 1
Interrupt Source
chapter.
S12P-Family Reference Manual, Rev. 1.13
Table 8-39. Interrupt Vectors
Section 8.3.2, “Register
NOTE
Table
CCR Mask
8-39), any of which can be individually masked
I bit
I bit
I bit
I bit
Freescale’s Scalable Controller Area Network (S12MSCANV3)
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
(CANTIER)”).
(CANCTL1)”).
Local Enable
Descriptions,” which details all
Resets and
(CANRIER)” to
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