S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 352

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

Pulse-Width Modulator (PWM8B6CV1) Block Description
10.4
10.4.1
There are four available clocks called clock A, clock B, clock SA (scaled A), and clock SB (scaled B).
These four clocks are based on the bus clock.
Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA
uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B
as an input and divides it further with a reloadable counter. The rates available for clock SA are software
selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. Similar rates are
available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the
pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB).
The block diagram in
10.4.1.1
The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze
mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze
mode the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM.
The input clock can also be disabled when all six PWM channels are disabled (PWME5–PWME0 = 0)
This is useful for reducing power by disabling the prescale counter.
Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A
and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value
selected for clock A is determined by the PCKA2, PCKA1, and PCKA0 bits in the PWMPRCLK register.
The value selected for clock B is determined by the PCKB2, PCKB1, and PCKB0 bits also in the
PWMPRCLK register.
352
PWM5ENA
PWM5INL
PWM5IN
Field
2
1
0
Functional Description
PWM Clock Select
PWM Channel 5 Input Status — This reflects the current status of the PWM5 pin.
PWM Shutdown Active Input Level for Channel 5 — If the emergency shutdown feature is enabled
(PWM5ENA = 1), this bit determines the active level of the PWM5 channel.
0 Active level is low
1 Active level is high
PWM Emergency Shutdown Enable — If this bit is logic 1 the pin associated with channel 5 is forced to input
and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if
PWM5ENA = 1.
0 PWM emergency feature disabled.
1 PWM emergency feature is enabled.
Prescale
Figure 10-34
Table 10-10. PWMSDN Field Descriptions (continued)
S12P-Family Reference Manual, Rev. 1.13
shows the four different clocks and how the scaled clocks are created.
Description
Freescale Semiconductor