S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 69

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

1. Read: Anytime
single-chip
single-chip
2.3.12
2.3.13
Freescale Semiconductor
Special
Normal
Write: Anytime
NCLKX2
Reset:
Address 0x001C
NECLK
DIV16
Field
EDIV
4-0
7
6
5
W
R
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate of equivalent to
the internal bus clock.
1 ECLK disabled
0 ECLK enabled
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK pre-divider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
NECLK
Depen-
ECLK Control Register (ECLKCTL)
PIM Reserved Register
Mode
dent
0
1
7
= Unimplemented or Reserved
NCLKX2
1
1
1
6
Table 2-12. ECLKCTL Register Field Descriptions
Figure 2-10. ECLK Control Register (ECLKCTL)
S12P-Family Reference Manual, Rev. 1.13
DIV16
0
0
0
5
EDIV4
0
0
0
4
Description
EDIV3
0
0
0
3
EDIV2
2
0
0
0
Port Integration Module (S12PPIMV1)
Access: User read/write
EDIV1
0
0
0
1
EDIV0
0
0
0
0
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