S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 190

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

S12S Debug Module (S12SDBGV2)
6.5.2
A trigger is generated if a given sequence of 3 code events is executed.
Scenario 1 is possible with S12SDBGV1 SCR encoding
6.5.3
A trigger is generated if a given sequence of 2 code events is executed.
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
190
SCR1=0011
SCR1=0011
SCR1=0111
SCR1=0010
State1
State1
State1
State1
Scenario 1
Scenario 2
M1
M1
M01
M2
SCR2=0010
SCR2=0101
SCR2=0101
SCR2=0011
State2
State2
State2
State2
S12P-Family Reference Manual, Rev. 1.13
Figure 6-28. Scenario 2a
Figure 6-29. Scenario 2b
Figure 6-30. Scenario 2c
Figure 6-27. Scenario 1
M2
M2
M2
M0
Final State
Final State
Final State
SCR3=0111
State3
M0
Final State
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