S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 438
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S9S12P64J0CFTR
Manufacturer Part Number
S9S12P64J0CFTR
Description
16-bit Microcontrollers - MCU 16-bit 64K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of S9S12P64J0CFTR
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
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128 KByte Flash Module (S12FTMRC128K1V1)
13.3.2.6
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
All assigned bits in the FERCNFG register are readable and writable.
438
Offset Module Base + 0x0005
IGNSF
Reset
FDFD
FSFD
Field
CCIE
7
4
1
0
W
R
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Force Single Bit Fault Detect
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
Flash Error Configuration Register (FERCNFG)
0
0
7
generated
Section
register is set (see
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section
13.3.2.8).
= Unimplemented or Reserved
13.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
13.3.2.6)
Figure 13-10. Flash Error Configuration Register (FERCNFG)
0
0
6
Section
Table 13-12. FCNFG Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
13.3.2.6)
0
0
5
—
The FSFD bit allows the user to simulate a single bit fault during Flash array
0
0
4
Description
0
0
3
0
0
2
Freescale Semiconductor
DFDIE
0
1
Section
Section
13.3.2.7)
SFDIE
13.3.2.7)
0
0
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